@other{https://resolver.caltech.edu/CaltechTHESIS:04122012-105252507, title = "Incorporating Time in the New World of Computing Systems", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-105252507", id = "record", doi = "10.7907/85gd-y881" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753, title = "anaLOG: A Functional Simulator for VLSI Neural Systems", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753", id = "record", doi = "10.7907/af3r-e056" } @other{https://resolver.caltech.edu/CaltechTHESIS:04132012-090947715, title = "Some Results on Kolmogorov-Chaitin Complexity", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-090947715", id = "record", doi = "10.7907/50qm-c858" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-104617758, title = "Sequential Threshold Circuits", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-104617758", id = "record", doi = "10.7907/fsx9-vh16" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-143033166, title = "Placement of Communicating Processes on Multiprocessor Networks", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-143033166", id = "record", doi = "10.7907/kemx-dv57" } @other{https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552, title = "HEX: A Hierarchical Circuit Extractor", url = "https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552", id = "record", doi = "10.7907/mptd-b683" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-161148552, title = "Supermesh", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-161148552", id = "record", doi = "10.7907/yvj1-jt57" } @other{https://resolver.caltech.edu/CaltechTHESIS:04022012-150108167, title = "Towards Concurrent Arithmetic: Residue Arithmetic and VLSI", url = "https://resolver.caltech.edu/CaltechTHESIS:04022012-150108167", id = "record", doi = "10.7907/mh9h-1v86" } @other{https://resolver.caltech.edu/CaltechTHESIS:04132012-084100294, title = "The General Interconnect Problem of Integrated Circuits", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-084100294", id = "record", doi = "10.7907/fgcc-ks03" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-093644670, title = "Design of the Mosaic Processor", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-093644670", id = "record", doi = "10.7907/cs85-zs74" } @other{https://resolver.caltech.edu/CaltechTHESIS:03272012-160759964, title = "Hierarchy of Graph Isomorphism Testing", url = "https://resolver.caltech.edu/CaltechTHESIS:03272012-160759964", id = "record", doi = "10.7907/pgav-zy26" } @other{https://resolver.caltech.edu/CaltechTHESIS:04092012-134858703, title = "Using Logic Programming for Compiling APL", url = "https://resolver.caltech.edu/CaltechTHESIS:04092012-134858703", id = "record", doi = "10.7907/gmjh-z702" } @other{https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759, title = "A VLSI Combinator Reduction Engine", url = "https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759", id = "record", doi = "10.7907/r471-je71" } @other{https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723, title = "FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723", id = "record", doi = "10.7907/vdzd-7h35" } @other{https://resolver.caltech.edu/CaltechTHESIS:04022012-150759898, title = "Hierarchical Nets: A Structured Petri Net Approach to Concurrency", url = "https://resolver.caltech.edu/CaltechTHESIS:04022012-150759898", id = "record", doi = "10.7907/t5w4-vt07" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185, title = "Type Inference in a Declarationless, Object-Oriented Language", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185", id = "record", doi = "10.7907/sa4t-bn94" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-091046970, title = "RTsim: A Register Transfer Simulator", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-091046970", id = "record", doi = "10.7907/727m-mf30" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092, title = "A Self-Timed Chip Set for Microprocessor Communication", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092", id = "record", doi = "10.7907/tnv1-t713" } @other{https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035, title = "EARL: An Integrated Circuit Design Language", url = "https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035", id = "record", doi = "10.7907/z452-0r86" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-100224959, title = "A Hierarchical Design Rule Checker", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-100224959", id = "record", doi = "10.7907/dqz1-c122" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-112531771, title = "A Versatile Ethernet Interface", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-112531771", id = "record", doi = "10.7907/x4t9-5n88" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952, title = "From Geometry to Logic", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952", id = "record", doi = "10.7907/887g-zn84" } @other{https://resolver.caltech.edu/CaltechTHESIS:03122018-162127158, title = "The Design and Implementation of a Reticle Maker for VLSI", url = "https://resolver.caltech.edu/CaltechTHESIS:03122018-162127158", id = "record", doi = "10.7907/0v5p-7011" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185, title = "REST: A Leaf Cell Design System", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185", id = "record", doi = "10.7907/1r9d-ad60" } @other{https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662, title = "Structure, Placement and Modelling", url = "https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662", id = "record", doi = "10.7907/tb24-mg70" } @other{https://resolver.caltech.edu/CaltechTHESIS:04122012-090812718, title = "Toward a Theorem Proving Architecture", url = "https://resolver.caltech.edu/CaltechTHESIS:04122012-090812718", id = "record", doi = "10.7907/ctky-sp95" } @other{https://resolver.caltech.edu/CaltechThesis:03092018-151643742, title = "Automated Wiring Analysis of Integrated Circuit Geometric Data", url = "https://resolver.caltech.edu/CaltechThesis:03092018-151643742", id = "record", doi = "10.7907/qxbg-2c10" } @other{https://resolver.caltech.edu/CaltechTHESIS:03122018-143833053, title = "A Pascal Machine Architecture Implemented in Bristle Blocks, a Prototype Silicon Computer", url = "https://resolver.caltech.edu/CaltechTHESIS:03122018-143833053", id = "record", doi = "10.7907/Z9VH5KTT" } @other{https://resolver.caltech.edu/CaltechTHESIS:04092012-133954577, title = "A VLSI Based Real-Time Hidden Surface Elimination Display System", url = "https://resolver.caltech.edu/CaltechTHESIS:04092012-133954577", id = "record", doi = "10.7907/Z9GF0RGD" }